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Microchip Technology /ATSAME70Q20 /PIOA /ODR

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Interpret as ODR

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https://regviz.com/r/Atmel/AT91SAM9G10/PIOB/ODR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (P0)P0 0 (P1)P1 0 (P2)P2 0 (P3)P3 0 (P4)P4 0 (P5)P5 0 (P6)P6 0 (P7)P7 0 (P8)P8 0 (P9)P9 0 (P10)P10 0 (P11)P11 0 (P12)P12 0 (P13)P13 0 (P14)P14 0 (P15)P15 0 (P16)P16 0 (P17)P17 0 (P18)P18 0 (P19)P19 0 (P20)P20 0 (P21)P21 0 (P22)P22 0 (P23)P23 0 (P24)P24 0 (P25)P25 0 (P26)P26 0 (P27)P27 0 (P28)P28 0 (P29)P29 0 (P30)P30 0 (P31)P31

Description

Output Disable Register

Fields

P0

Output Disable
P1

Output Disable
P2

Output Disable
P3

Output Disable
P4

Output Disable
P5

Output Disable
P6

Output Disable
P7

Output Disable
P8

Output Disable
P9

Output Disable
P10

Output Disable
P11

Output Disable
P12

Output Disable
P13

Output Disable
P14

Output Disable
P15

Output Disable
P16

Output Disable
P17

Output Disable
P18

Output Disable
P19

Output Disable
P20

Output Disable
P21

Output Disable
P22

Output Disable
P23

Output Disable
P24

Output Disable
P25

Output Disable
P26

Output Disable
P27

Output Disable
P28

Output Disable
P29

Output Disable
P30

Output Disable
P31

Output Disable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data